[Misc] Define HiSparse source readiness interface - #3

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Remove the module-local Torch facade and its native stream/context wrappers. Preserve Core event placement and add a changing-graph fork/join regression with CANN allocation. Generic/native component comparisons and extracted merged-Core stream methods passed on Ascend 950; complete package and model qualification remain pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Use MLAModules.index_group_builder for the model-owned group builder and remove the extra Ascend wrapper keyword. Preserve existing checkpoint, DCP, PP and post-load behavior. Source-isolated checks use actual merged Core modules/group builders and both constructor bodies; 16 configurations and 26 CPU regressions pass. This is not NPU or full-model qualification.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Reuse main explicit-dtype weight loading and Core private Host-pool defaults. Keep the necessary Core coordinator, shared-budget and view bridges. Remove synthetic loader/signature checks, consolidate capture and ordering coverage, and exercise real CPU workspace ownership. Sixteen CPU cases pass and all forty declared NPU combinations remain; full device/model qualification and full CI are still pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Reuse native SFA quantization and Attention, byte-capable scatter, and Core HMA/lifecycle ownership. Bind packed main rows and page-strided Indexer keys/scales without optional optimization profiles.

Add payload, addressing, alignment and eager/Graph regression coverage. Source-isolated CPU checks pass (23 cases); new-head NPU and full-model qualification remain pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Remove the embedded activation dump, generic stream probe, duplicate prefill and order checks, and mock-only Core forwarding tests. Reuse existing SFA preprocessing as the reference for one BF16/C8 destination test.

Retain device resolver/refill/invalidation, packed layouts and graph coverage. Production code and Attention kernels are unchanged. Twenty source-isolated CPU cases pass; NPU qualification remains pending.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Allow the BF16 bridge test to use the native SFA registration on A2, A3 and A5. Keep only the native E4M3FN C8 case restricted to A5 and skip the unregistered 310P operation. No production or kernel changes.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Remove AST extraction, dynamic exec/file loading and replacement base/spec classes. Exercise the actual backend inheritance, Core/Ascend cache specs and metadata builder through normal imports and the existing CPU-UT conftest.

Keep the same twenty boundary cases. Standard pytest was attempted but collection is blocked by missing local vllm dependencies; no source-isolated pass is claimed for this version. Focused syntax, Ruff, Markdown and diff checks pass.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Use a HiSparse Indexer subclass and the existing write_cache override. Restore ordinary Indexer write/build behavior and remove payload-format attributes and string routing. Reuse the cache backend choice in the model wrapper while retaining model-specific factories.

Keep the existing C8 stride helpers and native kernels unchanged. Update existing writer/wrapper tests; standard UT collection remains blocked by missing local vllm. Focused checks pass; full lint failed installing actionlint after a remote disconnect.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Place backend, binding, cache operations and C8 layout helpers in vllm_ascend/hisparse. Move the C8 native Attention invocation into AscendHiSparseImpl, which already owns its length workspace. Update the platform path and all consumers without compatibility forwarding modules.

Keep data transformations, allocator behavior, kernel arguments and native/Triton kernels unchanged. Existing C8 device coverage now enters the Attention backend. Packaging, syntax, focused lint and structural equivalence checks pass; standard UT and full lint remain blocked by local dependencies/tool installation.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

…allocation

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Keep Core lifecycle and Resident row mapping. Qualify this private candidate on NPU before publishing any performance claim.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Keep virtual refill rows separate and qualify bound HMA geometry. Leave Prefill mapping unchanged. Private candidate pending actual NPU and model qualification.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Call the native resolver directly from the existing owner-aware dispatch entry. Preserve all native arguments and runtime-owned scratch views.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Remove the capture-only stream wrapper after validating the fused resolver and refill with generic torch.Stream on Ascend950. Both wrapped and generic cross-stream cases pass, and the removal passes six resolver/refill and workspace rebind Graph cases.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Choose sorted invalidation from the table and write geometry, with a bounded sort buffer. Use the same selection during graph capture and verify changing writes on both single-stream and cross-stream replay.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Preserve the upstream Indexer metadata and PCP behavior alongside HiSparse physical page mapping and cache-role tests.

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

…ures

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Signed-off-by: zhenwenqi2024 <zhenwenqi_2022@qq.com>

Add the minimal worker-side Host writeback contract for the follow-up AscendStore pooling integration. This commit does not wire or change runtime behavior.

Signed-off-by: LifeOfCoffee <lcyzhyx@163.com>